View LTC1921_4230781.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 425112fc ltc4251/ltc4251-1/ ltc4251-2 typical a pplica t ion fea t ures descrip t ion negative voltage hot swap controllers in sot-23 a pplica t ions l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and hot swap and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n hot board insertion n electronic circuit breaker n C48v distributed power systems n negative power supply control n central office switching n programmable current limiting circuit n high availability servers n disk arrays n allows safe board insertion and removal from a live C48v backplane n floating topology permits very high voltage operation n programmable analog current limit with circuit breaker timer n fast response time limits peak fault current n programmable timer n programmable undervoltage/over voltage protection n low profile (1mm) thinsot? package the ltc ? 4251/ltc4251-1/ltc4251-2 negative voltage hot swap? controllers allow a board to be safely inserted and removed from a live backplane. output current is con- trolled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. the supply input is shunt regulated, allowing safe operation with very high supply voltages. a multifunction timer delays initial start-up and controls the circuit breakers response time. the ltc4251 uv/ov thresholds are designed to match the standard telecom operating range of C 43v to C75v. the ltc4251 - 1 uv /ov thresholds extend the operating range to encompass C36v to C72v. the ltc4251-2 implements a uv threshold of C43v only. all parts are available in the 6-pin sot-23 package. C48v, 2.5a hot swap controller start-up behavior gate 5v/div sense 2.5a/div v out 20v/div 425112 ta02 1ms/div + ltc4251 uv/ov timer gate sense v in v ee load ?48rtn ?48rtn (short pin) d in ? ddz13b** r1 402k 1% r c 10 r s 0.02 r2 32.4k 1% ?48v c t 150nf c1 10nf c c 18nf c in 1f c l 100f r in * 10k 500mw v out q1 irf530s 425112 ta01 4 3 2 1 *two 0.25w resistors in series for r in on the pcb are recommended. **diodes, inc. ?recommended for harsh environments not recommended for new designs please see ltc4251b for drop-in replacement
2 425112fc ltc4251/ltc4251-1/ ltc4251-2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings sense 1 v ee 2 v in 3 6 gate 5 uv/ov* 4 timer top view s6 package 6-lead plastic sot-23 *uv for ltc4251-2 t jmax = 125c, ja = 256c/w e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v z v in to v ee zener voltage i in = 2ma l 11.5 13 14.5 v r z v in to v ee zener dynamic impedance i in = 2ma to 30ma 5 i in v in supply current uv/ov = 4v, v in = (v z C 0.3v) l 0.8 2 ma v lko v in undervoltage lockout coming out of uvlo (rising v in ) l 9.2 11.5 v v lkh v in undervoltage lockout hysteresis 1 v v cb circuit breaker current limit voltage v cb = (v sense C v ee ) l 40 50 60 mv v acl analog current limit voltage v acl = (v sense C v ee ) l 80 100 120 mv v fcl fast current limit voltage v fcl = (v sense C v ee ) l 150 200 300 mv i gate gate pin output current uv/ov = 4v, v sense = v ee , v gate = 0v (sourcing) uv/ov = 4v, v sense C v ee = 0.15v, v gate = 3v (sinking) uv/ov = 4v, v sense C v ee = 0.3v, v gate = 1v (sinking) l 40 58 17 190 80 a ma ma v gate external mosfet gate drive v gate C v ee , i in = 2ma l 10 12 v z v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 2, 3) o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc4251cs6#pbf ltc4251cs6#trpbf ltuq 6-lead plastic sot-23 0c to 70c ltc4251is6#pbf ltc4251is6#trpbf ltur 6-lead plastic sot-23 C40c to 85c ltc4251-1cs6#pbf ltc4251-1cs6#trpbf ltqu 6-lead plastic sot-23 0c to 70c ltc4251-1is6#pbf ltc4251-1is6#trpbf ltqv 6-lead plastic sot-23 C40c to 85c ltc4251-2cs6#pbf ltc4251-2cs6#trpbf ltk6 6-lead plastic sot-23 0c to 70c ltc4251-2is6#pbf ltc4251-2is6#trpbf ltaaz 6-lead plastic sot-23 C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ current into v in (100s pulse) ............................. 100 ma minimum v in voltage ............................................ C 0.3v gate, uv/ov, timer voltage........................ C0.3v to 16v sense voltage ............................................ C 0.6v to 16v current out of sense pin (20s pulse) .............. C2 00ma maximum junction temperature .......................... 1 25c operating temperature range lt c4251c/ltc4251-1c/ltc4251-2c ........ 0 c to 70c lt c4251i/ltc4251-1i/ltc4251-2i ........ C 40c to 85c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) ................... 3 00c (note 1), all voltages are referred to v ee
3 425112fc ltc4251/ltc4251-1/ ltc4251-2 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions min typ max units v gatel gate low threshold (before gate ramp-up) 0.5 v v uvhi uv threshold high ltc4251/ltc4251-2 ltc4251-1 l l 3.075 2.300 3.225 2.420 3.375 2.540 v v v uvlo uv threshold low ltc4251/ltc4251-2 ltc4251-1 l l 2.775 2.050 2.925 2.160 3.075 2.270 v v v uvhst uv hysteresis ltc4251/ltc4251-2 ltc4251-1 0.30 0.26 v v v ovhi ov threshold high ltc4251 ltc4251-1 l l 5.85 5.86 6.15 6.17 6.45 6.48 v v v ovlo ov threshold low ltc4251 ltc4251-1 l l 5.25 5.61 5.55 5.91 5.85 6.21 v v v ovhst ov hysteresis ltc4251 ltc4251-1 0.60 0.26 v v i sense sense input current uv/ov = 4v, v sense = 50mv l C30 C15 a i inp uv/ov input current uv/ov = 4v l 0.1 1 a v tmrh timer voltage high threshold 4 v v tmrl timer voltage low threshold 1 v i tmr timer current timer on (initial cycle, sourcing), v tmr = 2v timer off (initial cycle, sinking), v tmr = 2v timer on (circuit breaker, sourcing), v tmr = 2v timer off (cooling cycle, sinking), v tmr = 2v 5.8 28 230 5.8 a ma a a t pllug uv low to gate low 0.7 s t phlog ov high to gate low ltc4251/ltc4251-1 1 s i in vs temperature i in vs v in r z vs temperature uv/ov = 4v refers to uv = 4v for the ltc4251-2. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ee unless otherwise specified. note 3: uv/ov = 4v refers to uv = 4v for the ltc4251-2. typical p er f or m ance c harac t eris t ics temperature (c) ?55 i in (a) 2000 1800 1600 1400 1200 1000 800 600 400 200 0 ?15 25 45 125 425112 g01 ?35 5 65 85 105 v in = (v z ? 0.3v) v in (v) 0 2 4 6 8 10 12 14 16 18 20 22 i in (ma) 1000 100 10 1 0.1 425112 g02 t a = ?40c t a = 125c t a = 25c t a = 85c temperature (c) ?55 r z () 10 9 8 7 6 5 4 3 2 ?15 25 45 125 425112 g03 ?35 5 65 85 105 i in = 2ma
4 425112fc ltc4251/ltc4251-1/ ltc4251-2 typical p er f or m ance c harac t eris t ics temperature (c) ?55 v z (v) 14.5 14.0 13.5 13.0 12.5 12.0 ?15 25 45 125 425112 g04 ?35 5 65 85 105 i in = 2ma temperature (c) ?55 v lko (v) 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 ?15 25 45 125 425112 g05 ?35 5 65 85 105 temperature (c) ?55 v lkh 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ?15 25 45 125 425112 g06 ?35 5 65 85 105 temperature (c) ?55 v cb (mv) 60 58 56 54 52 50 48 46 44 42 40 ?15 25 45 125 425112 g07 ?35 5 65 85 105 temperature (c) ?55 v acl (v) 120 115 110 105 100 95 90 85 80 ?15 25 45 125 425112 g08 ?35 5 65 85 105 temperature (c) ?55 v fcl (mv) 300 275 250 225 200 175 150 ?15 25 45 125 425112 g09 ?35 5 65 85 105 temperature (c) ?55 i gate (a) 70 65 60 55 50 45 40 ?15 25 45 125 425112 g10 ?35 5 65 85 105 uv/0v = 4v timer = 0v v sense = v ee v gate = 0v temperature (c) ?55 i gate (ma) 30 25 20 15 10 5 0 ?15 25 45 125 425112 g11 ?35 5 65 85 105 uv/0v = 4v timer = 0v v sense ? v ee = 0.15v v gate = 3v temperature (c) ?55 i gate (ma) 400 350 300 250 200 150 100 50 0 ?15 25 45 125 425112 g12 ?35 5 65 85 105 uv/0v = 4v timer = 0v v sense ? v ee = 0.3v v gate = 1v circuit breaker current limit voltage v cb vs temperature analog current limit voltage v acl vs temperature fast current limit voltage v fcl vs temperature i gate (source) vs temperature i gate (acl, sink) vs temperature i gate (fcl, sink) vs temperature uv/ov = 4v refers to uv = 4v for the ltc4251-2. v z vs temperature undervoltage lockout v lko vs temperature undervoltage lockout hysteresis v lkh vs temperature
5 425112fc ltc4251/ltc4251-1/ ltc4251-2 typical p er f or m ance c harac t eris t ics temperature (c) ?55 v gate (v) 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 ?15 25 45 125 425112 g13 ?35 5 65 85 105 uv/0v = 4v v tmr = 0v v sense = v ee temperature (c) ?55 v gatel (v) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?15 25 45 125 425112 g14 ?35 5 65 85 105 uv/0v = 4v, v tmr = 0v, gate threshold before ramp-up temperature (c) ?55 uv threshold (v) 3.375 3.275 3.175 3.075 2.975 2.875 2.775 ?15 25 45 125 425112 g15 ?35 5 65 85 105 v uvh ltc4251/ltc4251-2 v uvl temperature (c) ?55 uv threshold (v) 2.55 2.50 2.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 ?15 25 45 125 425112 g16 ?35 5 65 85 105 v uvhi ltc4251-1 v uvlo temperature (c) ?55 ov threshold (v) 6.45 6.25 6.05 5.85 5.65 5.45 5.25 ?15 25 45 125 425112 g17 ?35 5 65 85 105 v ovh ltc4251 v ovl temperature (c) ?55 ov threshold (v) 6.51 6.41 6.31 6.21 6.11 6.01 5.91 5.81 5.71 5.61 ?15 25 45 125 425112 g18 ?35 5 65 85 105 v ovhi v ovlo ltc4251-1 temperature (c) ?55 i sense (a) ?10 ?12 ?14 ?16 ?18 ?20 ?22 ?24 ?26 ?28 ?30 ?15 25 45 125 425112 g19 ?35 5 65 85 105 uv/0v = 4v timer = 0v gate = high v sense ? v ee = 50mv (v sense ? v ee ) (v) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?i sense (ma) 0.01 0.1 1.0 10 100 1000 425112 g20 uv/0v = 4v timer = 0v gate = high t a = 25c temperature (c) ?55 timer threshold (v) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?15 25 45 125 425112 g21 ?35 5 65 85 105 v tmrh v tmrl ov threshold vs temperature i sense vs temperature i sense vs (v sense ? v ee ) timer threshold vs temperature v gate vs temperature v gatel vs temperature uv threshold vs temperature uv threshold vs temperature ov threshold vs temperature uv/ov = 4v refers to uv = 4v for the ltc4251-2.
6 425112fc ltc4251/ltc4251-1/ ltc4251-2 typical p er f or m ance c harac t eris t ics temperature (c) ?55 i tmr (a) 10 9 8 7 6 5 4 3 2 1 0 ?15 25 45 125 425112 g22 ?35 5 65 85 105 temperature (c) ?55 i tmr (ma) 50 45 40 35 30 25 20 15 10 ?15 25 45 125 425112 g23 ?35 5 65 85 105 temperature (c) ?55 i tmr (a) 280 260 240 220 200 180 ?15 25 45 125 425112 g24 ?35 5 65 85 105 temperature (c) ?55 i tmr (a) 10 9 8 7 6 5 4 3 2 1 0 ?15 25 45 125 425112 g25 ?35 5 65 85 105 temperature (c) ?55 delay (s) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 ?15 25 45 125 425112 g26 ?35 5 65 85 105 t pllug t phlog (ltc4251/ltc4251-1) i tmr (cooling cycle, sinking) vs temperature t pllug and t phlog vs temperature i tmr (initial cycle, sourcing) vs temperature i tmr (circuit breaking, sourcing) vs temperature i tmr (initial cycle, sinking) vs temperature uv/ov = 4v refers to uv = 4v for the ltc4251-2.
7 425112fc ltc4251/ltc4251-1/ ltc4251-2 p in func t ions sense (pin 1): circuit breaker/current limit sense pin. load current is monitored by sense resistor r s connected between sense and v ee , and controlled in three steps. if sense exceeds v cb (50mv), the circuit breaker comparator activates a 230a timer pin pull-up current. the ltc4251/ ltc4251-1/ltc4251-2 latch off when c t charges to 4v. if sense exceeds v acl (100mv), the analog current limit amplifier pulls gate down and regulates the mosfet current at v acl /r s . in the event of a catastrophic short- circuit, sense may overshoot 100mv. if sense reaches v fcl (200mv), the fast current limit comparator pulls gate low with a strong pull-down. to disable the circuit breaker and current limit functions, connect sense to v ee . kelvin-sense connections between the sense resistor and the v ee and sense pins are strongly recommended, see figure 6. v ee (pin 2): negative supply voltage input. connect this pin to the negative side of the power supply. v in (pin 3): positive supply input. connect this pin to the positive side of the supply through a dropping resistor. a shunt regulator typically clamps v in at 13v. an internal undervoltage lockout (uvlo) circuit holds gate low until the v in pin is greater than v lko (9.2v), overriding uv/ov. if uv is high, ov is low and v in comes out of uvlo, timer starts an initial timing cycle before initiating a gate ramp up. if v in drops below approximately 8.2v, gate pulls low immediately. timer (pin 4): timer input. timer is used to generate a delay at start-up, and to delay shutdown in the event of an output overload. timer starts an initial timing cycle when the following conditions are met: uv is high, ov is low, v in clears uvlo, timer pin is low, gate is lower than v gatel and v sense C v ee < v cb . a pull-up current of 5.8a then charges c t , generating a time delay. if c t charges to v tmrh (4v) the timing cycle terminates, timer quickly pulls low and gate is activated. if sense exceeds 50mv while gate is high, a 230a pull-up current charges c t . if sense drops below 50mv before timer reaches 4v, a 5.8a pull-down current slowly discharges c t . in the event that c t eventually integrates up to the 4v v tmrh threshold, timer latches high with a 5.8a pull-up source and gate quickly pulls low. the ltc4251/ltc4251-1/ltc4251-2 fault latches may be cleared by either pulling timer low with an external device, or by pulling uv/ov below v uvlo . uv/ov (pin 5): undervoltage/overvoltage input. this dual function pin detects undervoltage as well as overvoltage. the high threshold at the uv comparator is set at v uvhi with v uvhst hysteresis. the high threshold at the ov comparator is set at v ovhi with v ovhst hysteresis. if uv/ ov < v uvlo or uv/ov > v ovhi , gate pulls low. if uv/ov > v uvhi and uv/ov < v ovlo , the ltc4251/ltc4251 - 1/ ltc4251-2 attempt to start-up. the internal uvlo at v in always overrides uv/ov. a low at uv resets an internal fault latch. a high at ov pulls gate low but does not reset the fault latch. a 1nf to 10nf capacitor at uv/ov eliminates transients and switching noise from affecting the uv/ov thresholds and prevents glitches at the gate pin. gate (pin 6): n-channel mosfet gate drive output. this pin is pulled high by a 58a current source. gate is pulled low by invalid conditions at v in (uvlo), uv/ov, or the fault latch. gate is actively servoed to control fault current as measured at sense. a compensation capacitor at gate stabilizes this loop. a comparator monitors gate to ensure that it is low before allowing an initial timing cycle, gate ramp up after an overvoltage event, or restart after a current limit fault. uv/ov refers to the uv pin for the ltc4251-2. the ov comparator in the ltc4251-2 is disabled. all references in the t ext to overvoltage, ov, v ovhi and v ovlo do not apply to the ltc4251-2.
8 425112fc ltc4251/ltc4251-1/ ltc4251-2 b lock diagra m ? + 425112 bd ? + ? + ? + ? + ? + ? + v in v in v in v ee v ee v ee v ee v ee v ee v ee 5.8a 5.8a 22a v in v in 58a 230a timer v ovhi v uvlo 4v 1v logic + ? + ? v ee v ee v os = 10mv 200mv ? + 0.5v uv/ov* ov** uv gate sense 6 1 2 3 5 4 5k cb fcl 50mv + ? acl *uv for the ltc4251-2 ** the ov comparator is disabled for ltc4251-2
9 425112fc ltc4251/ltc4251-1/ ltc4251-2 o pera t ion hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. the flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. the ltc4251/ ltc4251 - 1/ltc4251 - 2 are designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. initial start-up the ltc4251/ltc4251 - 1/l tc4251 - 2 reside on a removable circuit board and control the path between the connector and load or power conversion circuitry with an external mosfet switch (see figure 1). both inrush control and short-circuit protection are provided by the mosfet. a detailed schematic is shown in figure 2. C48v and C48rtn receive power through the longest connector pins, and are the first to connect when the board is inserted. the gate pin holds the mosfet off during this time. uv/ ov determines whether or not the mosfet should be turned on based upon internal, high accuracy thresholds and an external divider. uv/ov does double duty by also monitoring whether or not the connector is seated. the top of the divider detects C48rtn by way of a short connector pin that is the last to mate during the insertion sequence. interlock conditions a start-up sequence commences once five initial interlock conditions are met: 1. the input voltage v in exceeds 9.2v (v lko ) 2. the voltage at uv/ov falls within the range of v uvhi to v ovlo (uv > v uvhi , ltc4251 - 2) 3. the (sense C v ee ) voltage is <50mv (v cb ) 4. the voltage on the timer capacitor (c t ) is less than 1v (v tmrl ) 5. gate is less than 0.5v (v gatel ) the first two conditions are continuously monitored and the latter three are checked prior to initial timing or gate ramp-up. upon exiting an ov condition, the timer pin voltage requirement is inhibited. details are described in the applications information, timing waveforms section. timer begins the start-up sequence by sourcing 5.8a into c t . if v in or uv/ov falls out of range, the start-up cycle stops and timer discharges c t to less than 1v, then waits until the aforementioned conditions are once again met. if c t successfully charges to 4v, timer pulls low and gate is released. gate sources 58a (i gate ), charging the mosfet gate and associated capacitance. note that for simplicity, the following assumptions are made in the text. firstly , uv/ov also means the uv pin of the ltc4251-2. secondly, all overvoltage conditions and references to ov, v ovhi and v ovlo do not apply to the ltc4251-2 as the ov comparator in this part is disabled. 425112 f01 ltc4251 c load isolated dc/dc converter module low voltage circuitry + + ? ? plug-in board backplane ?48rtn ?48v + 34 12 425112 f02 ?48rtn ?48v uv/ov timer v ee v in sense gate ltc4251 r1 402k 1% r2 32.4k 1% c t 150nf c c 18nf r s 20m q1 irf530s r c 10 r in 10k 500mw c1 10nf c in 1f d in ? ddz13b** c l 100f typ long long short **diodes, inc. ?recommended for harsh environments + figure 1. basic ltc4251 hot swap topology figure 2. C48v , 2.5a hot swap controller
10 425112fc ltc4251/ltc4251-1/ ltc4251-2 two modes of operation are possible during the time the mosfet is first turning on, depending on the values of external components, mosfet characteristics and nomi- nal design current. one possibility is that the mosfet will turn on gradually so that the inrush into the load capacitance remains a low value. the output will simply ramp to C48v and the mosfet will be fully enhanced. a second possibility is that the load current exceeds the current limit threshold of 100mv/r s . in this case, the ltc4251/ltc4251 - 1/l tc4251 - 2 will ramp the output by sourcing 100mv/r s current into the load capacitance. it is important to set the timer delay so that, regardless of which start-up mode is used, the start-up time is less than the timer delay time. if this condition is not met, the ltc4251/ltc4251 - 1/l tc4251 - 2 may shutdown after one timer delay . board removal if the board is withdrawn from the card cage, the uv/ov divider is the first to lose connection. this shuts off the mosfet and commutates the flow of current in the con - nector. when the power pins subsequently separate, there is no arcing. current control three levels of protection handle short-circuit and over - load conditions. load current is monitored by sense and resistor r s . there are three distinct thresholds at sense: 50mv for a timed circuit breaker function; 100mv for an analog current limit loop; and 200mv for a fast, feedfor - ward comparator which limits peak current in the event of a catastrophic short-circuit. if, owing to an output overload, the voltage drop across r s exceeds 50mv, timer sources 230a into c t . c t eventually charges to a 4v threshold and the ltc4251/ltc4251 - 1/ l tc4251 - 2 latchoff. if the overload goes away and sense measures less than 50mv , c t slowly discharges (5.8a). o pera t ion in this way the circuit breaker function will also respond to low duty cycle overloads, and accounts for fast heating and slow cooling characteristic of the mosfet. higher overloads are handled by an analog current limit loop. if the drop across r s reaches 100mv, the current limiting loop servos the mosfet gate and maintains a constant output current of 100mv/r s . note that because sense > 50mv, timer charges c t during this time and the ltc4251/ltc4251 - 1/l tc4251 - 2 will eventually shut down. low impedance failures on the load side of the l tc4251/ ltc4251 - 1/l tc4251 - 2 coupled with 48v or more driving potential can produce current slew rates well in excess of 50a/s. under these conditions, overshoot is inevitable. a fast sense comparator with a threshold of 200mv detects overshoot and pulls gate low much harder and hence much faster than can the weaker current limit loop. the 100mv/r s current limit loop then takes over, and servos the current as previously described. as before, timer runs and latches the ltc4251/ltc4251 - 1/l tc4251 - 2 off when c t reaches 4v. the ltc4251/ltc4251 - 1/l tc4251 - 2 cir cuit breaker latch is reset by either pulling uv/ov momentarily low, or dropping the input voltage v in below the internal uvlo threshold of 8.2v. although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus, or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. the action of timer and c t rejects these events allowing the ltc4251/ltc4251 - 1/l tc4251 - 2 to ride out temporary overloads and disturbances that would trip a simple current comparator and in some cases, blow a fuse.
11 425112fc ltc4251/ltc4251-1/ ltc4251-2 s hunt r egulator a fast responding shunt regulator clamps the v in pin to 13v (v z ). power is derived from C48rtn by an external current limiting resistor, r in . a 1f decoupling capacitor, c in filters supply transients and contributes a short delay at start-up. to meet creepage requirements r in may be split into two or more series connected units, such as two 5.1k or three 3.3k resistors. this introduces a wider total spacing than is possible with a single component while at the same time ballasting the potential across the gap under each resistor. the ltc4251 is fundamentally a low voltage device that operates with C48v as its reference ground. to further protect against arc discharge into its pins, the area in and around the ltc4251 and all associated components should be free of any other planes such as chassis ground, return, or secondary-side power and ground planes. v in is rated handle 30ma within the thermal limits of the package, and is tested to survive a 100s, 100ma pulse. to protect v in against damage from higher amplitude spikes, clamp v in to v ee with a 13v zener diode. star connect v ee and all v ee referred components to the sense resistor kelvin terminal as illustrated in figure 2, keeping trace lengths between v in , c in , d in and v ee as short as possible. i nternal u nder voltage l ockout (uvlo) internal cir cuitry monitors v in for undervoltage. the exact thresholds are defined by v lko and its hysteresis, v lkh . when v in rises above 9.2v (v lko ) the chip is enabled; below 8.2v (v lko -v lkh ) it is disabled and gate is pulled low. the uvlo function at v in should not be confused with the uv/ov pin. these are completely separate functions. uv/ov c omp arators two hysteretic comparators for detecting under - and overvoltage conditions, with the following thresholds, monitor the dual function uv/ov pin: uv turning on at v uvhi uv turning off at v uvlo a pplica t ions i n f or m a t ion ov turning off at v ovhi ov turning on at v ovlo the uv and ov trip point ratio for ltc4251 is designed to match the standard telecom operating range of 43v to 75v. the ltc4251-2 implements a uv threshold of 43v only. a divider (r1, r2) is used to scale the supply voltage. using r1 = 402k and r2 = 32.4k gives a typical operating range of 43.2v to 74.4v. the under- and overvoltage shutdown thresholds are then 39.2v and 82.5v. 1% divider resis - tors are recommended to preserve threshold accuracy. the same resistor values can be used for the ltc4251-2. the r1-r2 divider values shown in the typical application set a standing current of slightly more than 100a, and define an impedance at uv/ov of 30k. in most applications, 30k impedance coupled with 300mv uv hysteresis makes the ltc4251/ltc4251-1/ltc4251-2 insensitive to noise. if more noise immunity is desired, add a 1nf to 10nf filter capacitor from uv/ov to v ee . the uv and ov trip point thresholds for the ltc4251 - 1 are designed to encompass the standard telecom operating range of C 36v to C72v. a divider (r1, r2) is used to scale the supply voltage. using r1 = 442k and r2 = 34.8k gives a typical operating range of 33.2v to 81v. the typical under- and overvoltage shutdown thresholds are then 29.6v and 84.5v. 1% divider resistors are recommended to preserve threshold accuracy. the r1-r2 divider values shown in the typical application set a standing current of slightly more than 100a, and define an impedance at uv/ov of 32k. in most applica - tions, 32k impedance coupled with 260mv uv hysteresis makes the ltc4251-1 insensitive to noise. if more noise immunity is desired, add a 1nf to 10nf filter capacitor from uv/ov to v ee . uv/ov o pera tion a low input to the uv comparator will reset the chip and pull the gate and timer pins low . a low-to-high uv transition will initiate an initial timing sequence if the three remaining interlock conditions are met.
12 425112fc ltc4251/ltc4251-1/ ltc4251-2 overvoltage conditions detected by the ov comparator will also pull gate low, thereby shutting down the load, but it will not reset the circuit breaker latch. returning the supply voltage to an acceptable range restarts the gate pin provided all interlock conditions except timer are met. timer the operation of the timer pin is somewhat complex as it handles several key functions. a capacitor, c t , is used at timer to provide timing for the ltc4251/ltc4251 - 1/ l tc4251 - 2. four different charging and discharging modes are available at timer: 1. 5.8a slow charge; initial timing delay 2. 230a fast charge; circuit breaker delay 3. 5.8a slow discharge; cir cuit breaker cool-off 4. low impedance switch; resets capacitor after initial timing delay, in under voltage lockout, and in overvoltage for initial startup, the 5.8a pull-up is used. the low im- pedance switch is turned off and the 5.8a current source is enabled when the four interlock conditions are met. c t charges to 4v in a time period given by: t = 4v ? c t 5.8a (1) when c t reaches 4v (v tmrh ), the low impedance switch turns on and discharges c t . the gate output is enabled and the load turns on. c ircuit b reaker timer o pera tion if the sense pin detects more than 50mv across r s , the timer pin charges c t with 230a. if c t charges to 4v, the gate pin pulls low and the ltc4251/ltc4251 - 1/ l tc4251 - 2 latch off. the part remains latched off until either the uv /ov pin is momentarily pulsed low, or v in dips into uvlo and is then restored. the circuit breaker timeout period is given by t = 4v ? c t 230a (2) intermittent overloads may exceed the 50mv threshold at sense, but if their duration is sufficiently short timer will not reach 4v and the ltc4251/l tc4251 - 1/l tc4251 - 2 will not latch off. to handle this situation, the timer discharges c t slowly with a 5.8a pull-down whenever the sense voltage is less than 50mv. therefore any in - termittent overload with an aggregate duty cycle of 2.5% or more will eventually trip the circuit breaker and latch off the ltc4251/ltc4251 - 1/l tc4251 - 2. figure 3 shows the cir cuit breaker response time in seconds normalized to 1f. the asymmetric charging and discharging of c t is a fair gauge of mosfet heating. a pplica t ions i n f or m a t ion gate gate is pulled low to v ee under any of the following conditions: in uvlo, during the initial timing cycle, in an overvoltage condition, or when the ltc4251/ltc4251 - 1/ l tc4251 - 2 are latched off after a short-cir cuit. when gate turns on, a 58a current source charges the mosfet gate and any associated external capacitance. v in limits gate drive to no more than 14.5v. gate-drain capacitance (c gd ) feed through at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the mosfet. a unique circuit pulls gate low with practically no usable voltage at v in , and eliminates current spikes at insertion. a large external gate-source capacitor is thus unnecessary for the purpose of compensating c gd . instead, a smaller value (10nf) capacitor c c is adequate. c c also provides compensation for the analog current limit loop. figure 3. circuit breaker response time fault duty cycle, d (%) 20 40 60 80 0 normalized response time (s/f) 10 1 0.1 0.01 100 425112 f03 t c t (f) 4 (235.8 ? d) C 5.8 =
13 425112fc ltc4251/ltc4251-1/ ltc4251-2 sense the sense pin is monitored by the circuit breaker (cb) comparator, the analog current limit (acl) amplifier, and the fast current limit (fcl) comparator. each of these three measures the potential of sense relative to v ee . if sense exceeds 50mv, the cb comparator activates the 230a timer pull-up. at 100mv, the acl amplifier servos the mosfet current, and at 200mv the fcl compara- tor abruptly pulls gate low in an attempt to bring the mosfet current under control. if any of these conditions persists long enough for timer to charge c t to 4v (see equation?(2)), the ltc4251/ltc4251 - 1/l tc4251 - 2 latch off and pull ga te low. if the sense pin encounters a voltage greater than 100mv, the acl amplifier will servo gate downwards in an attempt to control the mosfet current. since gate overdrives the mosfet in normal operation, the acl amplifier needs time to discharge gate to the threshold of the mosfet. for a mild overload, the acl amplifier can control the mosfet current, but in the event of a severe overload the current may overshoot. at sense = 200mv, the fcl comparator takes over, quickly discharging the gate pin to near v ee potential. fcl then releases, and the acl amplifier takes over. all the while timer is running. the effect of fcl is to add a nonlinear response to the control loop in favor of reducing mosfet current. owing to inductive effects in the system, fcl typically overcorrects the current limit loop, and gate undershoots. a zero in the loop (resistor r c in series with the gate capacitor) helps the acl amplifier recover. s hor t -c ircuit o pera tion circuit behavior arising from a load-side low impedance short is shown in figure 4. initially, the current overshoots the analog current limit level of v sense = 100mv (trace 2) as the gate pin works to bring v gs under control (trace?3). the overshoot glitches the backplane in the negative direction, and when the current is reduced to 100mv/r s the backplane responds by glitching in the positive direction. timer commences charging c t (trace 4) while the analog current limit loop maintains the fault current at 100mv/r s , which in this case is 5a (trace 2). note that the backplane voltage (trace 1) sags under load. when c t reaches 4v, gate turns off, the load current drops to zero and the backplane rings up to over 100v. the positive peak is usually limited by avalanche breakdown in the mosfet, and can be further limited by adding a transient voltage suppressor across the input from C 48v to C48rtn, such as diodes inc. smat70a. a low impedance short on one card may influence the behavior of others sharing the same backplane. the initial glitch and backplane sag as seen in figure 4, trace 1, can rob charge from output capacitors on adjacent cards. when the faulty card shuts down, current flows in to refresh the capacitors. if ltc4251, ltc4251-1 or ltc4251 - 2s are used throughout, they respond by limiting the inrush current to a value of 100mv/r s . if c t is sized correctly, the capacitors will recharge long before c t times out. a pplica t ions i n f or m a t ion mosfet s election the external mosfet switch must have adequate safe operating area (soa) to charge the load capacitance on start-up and handle short-circuit conditions until timer latchoff. these considerations take precedence over dc current ratings. a mosfet with adequate soa for a given application can always handle the required current, but the opposite cannot be said. consult the manufacturers mosfet data sheet for safe operating area and effective transient thermal impedance curves. figure 4. output short-circuit behavior (all waveforms are referenced to v ee) gate 10v/div sense 200mv/div ?48rtn 50v/div timer 5v/div 425112 f04 supply ring owing to current overshoot supply ring owing to mosfet turn-off onset of output short-circuit fast current limit analog current limit c timer ramp latch off trace 1 trace 2 trace 3 trace 4 2ms/div
14 425112fc ltc4251/ltc4251-1/ ltc4251-2 mosfet selection is a three-step process. first, r s is calculated, and then the time required to charge the load capacitance is determined. this timing, along with the maximum short-circuit current and maximum input volt - age defines an operating point that is checked against the mosfets soa curve. to begin a design, first specify the required load current and load capacitance, i l and c l . the circuit breaker current trip point (50mv/r s ) should be set to accommodate the maximum load current. note that maximum input current to a dc/dc converter is expected at v supply (min) . r s is given by: r s = 40mv i l(max) (3) where 40mv represents the guaranteed minimum circuit breaker threshold. during the initial charging process, the ltc4251/ ltc4251 - 1/l tc4251 - 2 may operate the mosfet in current limit, forcing 80mv to 120mv across r s . the minimum inrush current is given by: i inrush(min) = 80mv r s (4) maximum short-circuit current limit is calculated using maximum v sense , or: i short-circuit(max) = 120mv r s (5) the timer capacitor c t must be selected based on the slowest expected charging rate; otherwise timer might time out before the load capacitor is fully charged. a value for c t is calculated based on the maximum time it takes the load capacitor to charge. that time is given by: t cl charge = c ? v i = c l ? v supply(max) i inrush(min) (6) substituting equation (4) for i inrush(min) and equating (6) with (2) gives: c t = c l ? v supply (max) ? r s ? 230a (4v ? 80mv) (7) returning to equation (2), the timer period is calcu- lated and used in conjunction with v supply(max) and i short - circuit(max) to check the soa curves of a prospec - tive mosfet. as a numerical design example, consider a 30w load, which requires 1a input current at 36v. if v supply(max) = 72v and c l = 100f, equation (3) gives r sense = 40m; equation (7) gives c t = 207nf. to account for errors in r sense , c t , timer current (230a) and timer threshold (4v), the calculated value should be multiplied by 1.5, giving a nearest standard value of c t = 330nf. if a short-circuit occurs, a current of up to 120mv/40m = 3a will flow in the mosfet for 5.7ms as dictated by c t = 330nf in equation (2). the mosfet must be selected based on this criterion. the irf530s can handle 100v and 3a for 10ms, and is safe to use in this application. s ummar y of d esign f low to summarize the design flow , consider the application shown in figure 2, which was designed for 50w: calculate maximum load current: 50w/36v = 1.4a; allow- ing 83% converter efficiency, i in (max) = 1.7a. calculate r s : from equation (3) r s = 20m. calculate c t : from equation (7) c t = 150nf (including 1.5x correction factor). calculate timer period: from equation (2) the short-circuit time-out period is t = 2.6ms. calculate maximum short-circuit current: from equation (5) maximum short-circuit current could be as high as 120mv/20m = 6a. consult mosfet soa curves: the irf530s can handle 6a at 72v for 5ms, so it is safe to use in this application. a pplica t ions i n f or m a t ion
15 425112fc ltc4251/ltc4251-1/ ltc4251-2 frequency compensation the ltc4251/ltc4251 - 1/ ltc4251 - 2 typical frequency compensation network for the analog current limit loop is a series r c (10) and c c connected to v ee . figure 5 depicts the relationship between the compensation ca- pacitor c c and the mosfets c iss . the line in figure 5 is used to select a starting value for c c based upon the mosfets c iss specification. optimized values for c c are shown for several popular mosfets. differences in the optimized value of c c versus the starting value are small. nevertheless, compensation values should be verified by board level short-circuit testing. as seen in figure 4 previously, at the onset of a short- circuit event, the input supply voltage can ring dramatically owing to series inductance. if this voltage avalanches the mosfet, current continues to flow through the mosfet to the output. the analog current limit loop cannot control this current flow and therefore the loop undershoots. this effect cannot be eliminated by frequency compensation. a zener diode is required to clamp the input supply voltage and prevent mosfet avalanche. resistor. pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. a pplica t ions i n f or m a t ion sense resistor considerations for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the v ee and sense pins are strongly recommended. the drawing in figure 6 illustrates the correct way of making connections between the ltc4251/ltc4251 - 1/l tc4251 - 2 and the sense t iming w aveform s system power -up figure 7 details the timing waveforms for a typical power-up sequence in the case where a board is already installed in the backplane and system power is applied abruptly. at time point 1, the supply ramps up, together with uv/ov and v out . v in follows at a slower rate as set by the v in bypass capacitor. at time point 2, v in exceeds v lko and the internal logic checks for v uvhi < uv/ov < v ovlo , timer < v tmrl , gate < v gatel and sense < v cb . when all conditions are met, an initial timing cycle starts and the timer capacitor is charged by a 5.8a current source pull-up. at time point 3, timer reaches the v tmrh threshold and the initial timing cycle terminates. the timer capacitor is then quickly discharged. at time point 4, the v tmrl threshold is reached and the conditions of gate < v gatel and sense < v cb must be satisfied before a start-up cycle is allowed to begin. gate sources 58a into the external mosfet gate and compensation network. when the gate voltage reaches the mosfets threshold, current begins flowing into the load capacitor. at time point 5, the sense voltage (v sense C v ee ) reaches the v cb threshold and activates the timer. the timer capacitor mosfet c iss (pf) compensation capacitor c c (nf) 425112 f05 60 50 40 30 20 10 0 0 2000 4000 6000 8000 irf530 irf540 irf740 irf3710 mty100n10e figure 5. recommended compensation capacitor c c vs mosfet c iss w current flow from load current flow to ?48v backplane sense resistor track width w: 0.03" per amp on 1 oz copper to sense to v ee 425112 f06 figure 6. making pcb connections to the sense resistor
16 425112fc ltc4251/ltc4251-1/ ltc4251-2 is charged by a 230a current-source pull-up. at time point 6, the analog current limit loop activates. between time point 6 and time point 7, the gate voltage is held essentially constant and the sense voltage is regulated at v acl . as the load capacitor nears full charge, its current begins to decline. at point 7, the load current falls and the sense voltage drops below v acl . the analog current limit loop shuts off and the gate pin ramps further. at time point 8, the sense voltage drops below v cb and timer now discharges through a 5.8a current source pull-down. at time point 9, gate reaches its maximum voltage as determined by v in . live insertion with short pin control of uv/ov in this example as shown in figure 8, power is delivered through long connector pins whereas the uv/ov divider makes contact through a short pin. this ensures the power connections are firmly established before the ltc4251/ ltc4251 - 1/l tc4251 - 2 are activated. at time point 1, the power pins make contact and v in ramps through v lko . at time point? 2, the uv/ov divider makes contact and its voltage exceeds v uvhi . in addition, the internal logic checks for v uvhi < uv/ov < v ovhi , timer < v tmrl , gate < v gatel and sense < v cb . when all conditions are met, an initial timing cycle starts and the timer capacitor is charged by a 5.8a current source pull-up. at time point 3, timer reaches the v tmrh threshold and the ini- tial timing cycle terminates. the timer capacitor is then quickly discharged. at time point 4, the v tmrl threshold is reached and the conditions of gate < v gatel and sense < v cb must be satisfied before a start-up cycle is allowed to begin. gate sources 58a into the external mosfet gate and compensation network. when the gate voltage reaches the mosfets threshold, current begins flowing into the load capacitor. at time point 5, the sense voltage (v sense C v ee ) reaches the v cb threshold and activates the timer. the timer capacitor is charged by a 230a current source pull-up. at time point 6, the analog current limit loop activates. between time point 6 and time point 7, the gate voltage is held essentially constant and the sense voltage is regulated at v acl . as the load capacitor nears full charge, its current begins to a pplica t ions i n f or m a t ion decline. at time point 7, the load current falls and the sense voltage drops below v acl . the analog current limit loop shuts off and the gate pin ramps further. at time point 8, the sense voltage drops below v cb and timer now discharges through a 5.8a current source pull-down. at time point 9, gate reaches its maximum voltage as determined by v in . undervoltage lockout timing in figure 9, when uv/ov drops below v uvlo (time point 1), timer and gate pull low. if current has been flowing, the sense pin voltage decreases to zero as gate collapses. when uv/ov recovers and clears v uvhi (time point 2), an initial time cycle begins followed by a start-up cycle. undervoltage timing with overvoltage glitch in figure 10, when uv/ov clears v uvhi (time point 1), an initial timing cycle starts. if the system bus voltage overshoots v ovhi as shown at time point 2, timer dis- charges. at time point 3, the supply voltage recovers and drops below the v ovlo threshold. the initial timing cycle restarts followed by a start-up cycle. overvoltage timing during normal operation, if uv/ov exceeds v ovhi as shown at time point 1 of figure 11, the timer status is unaffected. nevertheless, gate pulls down and discon - nects the load. at time point 2, uv/ov recovers and drops below the v ovlo threshold. a gate ramp up cycle ensues. if the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle may occur as shown between time points 3 through 6. timer behavior in figure 12a, the timer capacitor charges at 230a if the sense pin exceeds v cb . it is discharged with 5.8a if the sense pin is less than v cb . in figure 12b, when timer exceeds v tmrh , timer is latched high by the 5.8a pull-up and gate pulls down immediately. in figure 12c, multiple momentary faults cause the timer capacitor to integrate until it latches.
17 425112fc ltc4251/ltc4251-1/ ltc4251-2 a pplica t ions i n f or m a t ion 1 3 2 4 5 6 7 8 9 v in clears v lko , check v uvhi 18 425112fc ltc4251/ltc4251-1/ ltc4251-2 a pplica t ions i n f or m a t ion analog current limit and fast current limit in figure 13a, when sense exceeds v acl , gate is regulated by the analog current limit amplifier loop. when sense drops below v acl , gate is allowed to pull up. in figure 13b, when a severe fault occurs, sense exceeds v fcl and gate immediately pulls down until the analog current amplifier can establish control. if timer reaches v tmrh , gate pulls low and latches off. resetting a fault latch as shown in figure 14, a latched fault is reset by either pulling uv/ov below v uvlo or pulling timer below v tmrl . an initial timing cycle is initiated if uv/ov is used for reset. if timer is used for reset, the initial timing cycle is skipped. internal soft-start an internal soft-start feature ramps the positive input of the analog current limit amplifier during initial start-up. the ramp duration is approximately 200s. this feature reduces load current dl/dt at start-up. as illustrated in figure?15, soft-start is initiated by a timer transition from v tmrh to v tmrl or when uv/ov falls below the v ovlo threshold after an ov fault. after soft-start duration, load current is limited by v acl /r s . figure 9. undervoltage lockout timing (all waveforms are referenced to v ee ) 1 3 2 4 5 6 7 8 9 v uv/0v clears v uvhi , check timer < v tmrl , gate < v gatel and sense < v cb . v uv/0v drops below v uvlo . timer, gate, and sense are pulled to v ee . timer clears v tmrl , check gate < v gatel and sense < v cb . v uvhi v uvlo v tmrh v tmrl v acl v cb 5.8a 230a 58a 58a 5.8a 5.8a initial timing cycle start-up cycle 425112 f09 uv/0v timer gate sense
19 425112fc ltc4251/ltc4251-1/ ltc4251-2 a pplica t ions i n f or m a t ion figure 10. undervoltage timing with an overvoltage glitch (all waveforms are referenced to v ee ) 1 3 2 4 5 6 7 8 9 v uv/0v drops below v ovlo and timer restarts initial timing cycle. v uv/0v clears v uvhi . check timer < v tmrl , gate < v gatel and sense < v cb . v uv/0v overshoots v ovhi and timer aborts initial timing cycle. timer clears v tmrl , check gate < v gatel and sense < v cb . v ovhi v uvhi v ovlo v tmrh v tmrl v acl v cb 5.8a 230a 58a 58a 5.8a 5.8a initial timing cycle start-up cycle 425112 f10 uv/0v timer gate sense 10 1 32 4 5 6 7 uv/0v timer gate sense v ovhi v tmrh v ovlo v acl v cb 5.8a 5.8a 5.8a 5.8a 425112 f11 230a 58a 58a v uv/0v drops below v ovlo and gate restarts. v uv/0v overshoots v ovhi and gate pulls to v ee . timer unaffected. figure 11. overvoltage timing (all waveforms are referenced to v ee )
20 425112fc ltc4251/ltc4251-1/ ltc4251-2 a pplica t ions i n f or m a t ion timer gate sense v out v acl v tmrl v cb 5.8a 5.8a cb fault 230a 1 2 425112 f12a timer gate sense v out v acl v tmrh v cb 5.8a cb fault 230a 1 2 timer latches off 425112 f12b timer gate sense v out v acl v tmrh v cb 5.8a 5.8a 230a 230a 1 4 3 2 timer latches off 425112 f12c (12a) momentary circuit-breaker fault (12b) circuit-breaker time-out figure 12. timer behavior (all waveforms are referenced to v ee ) (12c) multiple circuit-breaker faults
21 425112fc ltc4251/ltc4251-1/ ltc4251-2 timer gate sense v out v acl v tmrh v cb 58a 5.8a 5.8a 1 432 230a 425112 f13a timer gate sense v out v fcl v acl v tmrh v cb 5.8a 230a 1 2 timer latches off 425112 f13b timer gate sense v acl v tmrh v tmrl v cb 5.8a 5.8a 5.8a 1 5 6432 230a 58a 58a reset latched timer fault by external low pulse. 425112 f14 timer gate sense v acl v acl + 10mv v tmrh v tmrl ~v gs(th) v cb 5.8a 1 4 5 6 32 230a internal soft-start reference 58a 10mv end of initial timing cycle 425112 f15 figure 13. current limit behavior (all waveforms are referenced to v ee ) (13a) analog current limit fault (13b) fast current limit fault figure 14. latched fault reset timing (all waveforms are referenced to v ee ) figure 15. internal soft-start timing (all waveforms are referenced to v ee ) a pplica t ions i n f or m a t ion
22 425112fc ltc4251/ltc4251-1/ ltc4251-2 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
23 425112fc ltc4251/ltc4251-1/ ltc4251-2 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 3/11 revised typical application drawings replaced shunt regulator section in applications information section revised short-circuit operation section 1, 24 11 13 c 3/12 not recommended for new designs 1 (revision history begins at rev b)
24 425112fc ltc4251/ltc4251-1/ ltc4251-2 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2001 lt 0312 rev c ? printed in usa r ela t e d p ar t s typical a pplica t ions part number description comments lt1640ah/lt1640al negative high voltage hot swap controllers in so-8 negative high voltage supplies from C10v to C80v lt1641-1/lt1641-2 positive high voltage hot swap controllers in so-8 supplies from 9v to 80v, latched off/autoretry ltc1642 fault protected hot swap controller 3v to 16.5v, overvoltage protection up to 33v LTC1921 dual C 48v supply and fuse monitor 1v uv and 1.5v ov threshold accuracy, 200v transient protection, drives three optoisolators for status lt4250 C48v hot swap controller in so-8 active current limiting, supplies from C20v to C80v ltc4252-1/ ltc4252-2 negative voltage hot swap controller in msop fast active current limiting with drain accelerated response, supplies from C15v ltc4253 negative voltage hot swap controller with 3-output sequencer fast active current limiting with drain accelerated response, supplies from C15v + ltc4251 uv/ov timer gate sense v in v ee 1 2 3 4 5 6 load ?48rtn ?48rtn (short pin) r1 402k 1% r c 10 r s 0.01 r3 22 r2 32.4k 1% ?48v c t 82nf c1 10nf c c 22nf c in 1f c l 100f r in 10k 500mw q1 irf540 425112 ta03 push- reset s1 4 3 2 1 **diodes, inc. ?recommended for harsh environments d in ? ddz13b** + ltc4251-1 uv/ov timer gate sense v in v ee 1 2 3 4 5 6 load ?48rtn ?48rtn (short pin) r1 442k 1% r c 10 r s 0.02 r2 34.8k 1% ?48v c t 220nf c1 10nf c c 22nf c in 1f d1 bzx84c36 c l 100f r in 10k 500mw r3 31.6k r4 22 v out q1 irf540s 425112 ta04 4 3 2 1 **diodes, inc. ?recommended for harsh environments d in ? ddz13b** figure 16. C48v/5a application with reverse sense pin limiting and push-reset at timer pin figure 17. power-limited circuit breaker application

▲Up To Search▲

Price & Availability of LTC1921

	To Download LTC1921 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .